1. Field of the Invention
The present invention relates to a refresh period generating circuit for generating a refresh period in a DRAM product (for example, including general-purpose DRAM, SDRAM, pseudo SRAM, and system LSI installed with DRAM) having the auto refresh function on a memory cell (hereinafter, referred to as a DRAM cell) of DRAM (Dynamic Random Access Memory).
2. Related Art
A DRAM cell is comprised of a capacitor that stores an electrical charge as data and a transistor that switches between input and output of the data. The data retention characteristics of the DRAM cell have extremely large temperature dependence as compared with electrical characteristics of other structural elements such as, for example, a MOS transistor. The electrical characteristics of other structural elements are generally dependent on the temperature dependence of the mobility of electrons. It is known that an increase in temperature by 10° C. makes delay of about 5% in characteristics. Meanwhile, the data retention characteristics of the DRAM cell are principally dependent on junction leakage between a N-type diffusion layer and P-type diffusion layer constituting part of the DRAM cell. It is known that the data retention characteristics (data retention time) become about half as the temperature increases by 10° C.
In recent years, it has become general that widespread portable devices are miniaturized and configured to enable backup by battery. Therefore, the portable devices facilitate their portability. With respect to DRAM products for use in such a type of portable device, self refresh to automatically perform refresh is introduced, and the load on the system can thereby be reduced. As a configuration to perform self refresh, a refresh timer is provided for the DRAM product to perform periodic refresh, an address (word-line address) and clock for refresh is internally generated at the designated time, and refresh is performed automatically.
Particularly at the self refresh time, the portable device usually does not operate, thereby does not exhibit heating, and in consideration of carrying the device, it is assumed that the actual use temperature or the ambient temperature is about room temperature. Therefore, since the data retention time is long at room temperature (at low temperatures), the self refresh period is made longer than that at high temperatures, and thus, the device is provided with the temperature compensation function for refresh to reduce power consumption due to refresh operation.
As the temperature compensation function for refresh, various methods are described in JP 2002-215258 (however, this document discloses compensation examples to eliminate the temperature dependence). FIG. 9 shows a configuration example of a conventional analog-system refresh period generating circuit as an oscillation circuit for varying the oscillation period in analog form by high magnification corresponding to temperature. The configuration of FIG. 9 is suitable for, particularly, temperature compensation for the refresh period with the large temperature dependence. A refresh period generating circuit 100 as shown in FIG. 9 is provided with a band-gap type reference voltage generating circuit (VREF0) 011, a comparative voltage generating circuit (VREF1) 012, a current control signal generating circuit (CSGEN) 013 with positive temperature dependence, and a ring oscillator (R-OSC) 014 as an oscillator.
In the aforementioned configuration, the band-gap type reference voltage generating circuit 011 outputs voltage VBGR with no temperature dependence and voltage VBE with temperature dependence. The comparative voltage generating circuit 012 receives as its input the voltage VBGR with no temperature dependence, and based on the voltage VBGR, generates comparative voltage VRTR0 with no temperature dependence suitable for comparison. The current control signal generating circuit 013 receives the voltage VBE and comparative voltage VRTR0 to compare, generates current control signals OSCBP and OSCBN, and inputs both the signals to the ring oscillator 014. The ring oscillator 014 is configured to control the oscillating frequency using the current control signals OSCBP and OSCBN and output a refresh reference signal REFRQ. The signal REFRQ works as a control signal for refresh.
In addition, assuming that the refresh period is Tref, a minimum cycle allowing refresh is Trcyc, a current flowing when refresh is continued successively at the minimum cycle is Iref, and a standby current is Istb, a current Iself at the self refresh time is expressed as follows:Iself=(Iref)×(Trcyc/Tref)+IstbThus, the level is of the order of 250 μA in terms of the capability of the DRAM product. It is necessary to limit the standby current Istb to substantially 20 to 25 μA, and power consumption in refresh period generating circuit 100 is thereby restricted.
FIG. 10 is a graph illustrating the relationship between temperature and refresh period in the analog-system refresh period generating circuit 100 as shown in FIG. 9. In the graph of FIG. 10, the horizontal axis represents temperature, while the vertical axis represents normalized period. In the graph of FIG. 10, a line 021 shows the temperature dependence of the data retention characteristics (refresh period required for data retention) in a typical DRAM cell, while a curve 022 shows the temperature dependence of the refresh period in the refresh period generating circuit 100 as shown in FIG. 9. As can be seen from the curve 022, the temperature dependence decreases and becomes saturated at high temperatures and low temperatures. This is because the control current (described later) in the ring oscillator 014 becomes a constant value and does not vary at upper limit or lower limit. To vary the refresh period in analog form, it is possible to set the temperature such that the temperature dependence becomes saturated at high temperatures or low temperatures at an arbitrary temperature to some extent by design.
However, in the configuration of the analog-system refresh period generating circuit 100, since the oscillating frequency is varied by only a few times at the maximum, the temperature range that can be covered is narrowed. In other words, in the case of considering 0.5 times/10° C. as the temperature dependence of the data retention time of the DRAM cell, the temperature range that can be covered is only from 20° C. to 30° C., and it is difficult to sufficiently reduce the current consumption at low temperatures. Moreover, to further reduce AC operation part (dynamic current) of current consumption at low temperatures in half, it is required to further reduce a variation range of the oscillating frequency to lower frequencies particularly at low temperatures, but such reduction is difficult. Thus, the conventional analog-system refresh period generating circuit 100 has problems in terms of power reduction of the DRAM product for use in the portable device.
Meanwhile, instead of varying the refresh period in analog form as described above, a configuration is known that varies the refresh period in digital form. An example of the digital-system refresh period generating circuit with such a configuration is disclosed in JP H05-307882.
FIG. 11 shows a configuration example of a conventional digital-system refresh period generating circuit as an oscillation circuit that varies the oscillation period in digital form corresponding to temperature. A refresh period generating circuit 200 as shown in FIG. 11 is comprised of a ring oscillator (R-OSC) 014, a dividing circuit (DIVIDER) 015, a temperature sensor (TEMP-SENSOR) 016 and a frequency selector (SELECTOR) 017.
In the aforementioned configuration, an oscillation output of the ring oscillator 014 is input to the dividing circuit 015, and the frequency selector 017 selects among divided frequencies (division outputs) using a signal to identify the temperature obtained in the temperature sensor 016, and outputs a refresh reference signal REFRQ.
For example, such a constitution is considered that the dividing circuit 015 is a binary counter, and temperature detection is carried out in steps of 10° C., the most significant bit of the binary counter is selected at the minimum detection temperature, and then, lower bit of the binary counter is selected sequentially whenever the temperature increases by one step. Such a constitution reduces the refresh period in half whenever the temperature increases by 10° C., corresponds to that the data retention time of the DRAM cell is reduced in half with a 10° C. increase in temperature as described previously, and thus is convenient. However, to vary in what temperature step is dependent on the performance the temperature selector and a processing method of the divided signal, and is selected by design.
FIG. 12 is a graph illustrating the relationship between temperature and refresh in the digital-system refresh period generating circuit 200 as shown in FIG. 11. In the graph of FIG. 12, the horizontal axis represents temperature, while the vertical axis represents normalized period. In the graph of FIG. 12, a line 021 shows the temperature dependence of the data retention characteristics in a typical DRAM cell, while a solid line 023 shows the temperature dependence of the refresh period in the refresh period generating circuit 200 as shown in FIG. 11. Assuming that the refresh period is designed to vary by one-fourth times every 20° C., since the frequency is the reciprocal of the period, the refresh frequency varies by four times every 20° C. Further, a broken line 024 shows a range of fluctuations of the oscillating frequency or period due to fluctuations of accuracy in frequency switching in the temperature sensor 016, fluctuations in manufacturing process and the like.
It is generally known that in an integrated circuit a relative value is obtained with relatively high accuracy, but an absolute value greatly varies depending on manufacturing conditions. For example, detecting the temperature in steps of 10° C. or making the frequency two times or half is of relative value, and can be implemented with high accuracy. In contrast thereto, for example, detecting 70° C. or outputting a frequency of 100 kHz is of absolute value, and may cause fluctuations of 20% to 30%. In particular, since the idea of varying the refresh period originates from reduction in current consumption when the temperature is low, it is useless trading off an increase in current consumption for suppression of fluctuations.
In other words, a region indicated by the broken line 024 in FIG. 12 represents a range of variations in the characteristics due to process fluctuations, and is close to the limit of data retention characteristics of the line 021 at a switching portion of the refresh period, i.e. a corner portion of the stepwise waveform of the line 023. Accordingly, when effects are considered such as variations in design value, manufacturing parameter and the like, the possibility is assumed that the refresh period is increased exceeding the limit of the data retention characteristics, and data of the DRAM cell is lost. In order to deal with such a phenomenon, it is necessary to secure a wide operation margin in refresh. Such a margin increases the number of refresh times, and current consumption increases.
As described above, in the conventional refresh period generating circuits, when decreasing the frequency of refresh to reduce power consumption, particularly power consumption at low temperatures in self refresh of the DRAM product, there have been defects that a variation amount of the frequency is small in the analog system that provides the frequency with temperature dependence, and that the digital system that provides a large variation in frequency with temperature causes the possibility that the refresh period exceeds a required value at a corner portion of the frequency switching or the like, and to prevent such a possibility, requires a wide operation margin.